View MAX1620_155359.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-1214; Rev 1; 1/98
NUAL KIT MA T ATION A SHEE EVALU S DAT OLLOW F
Digitally Adjustable LCD Bias Supplies
General Description
The MAX1620/MAX1621 convert a 1.8V to 20V battery voltage to a positive or negative LCD backplane bias voltage. Backplane bias voltage can be automatically disabled when the display logic voltage is removed, protecting the display. These devices use very little PC board area, come in ultra-small QSOP packages, and require only small, low-profile external components. Output voltage can be set to a desired positive or negative voltage range with external resistors, and adjusted over that range with the on-board digital-to-analog converter (DAC) or with a potentiometer. The MAX1620/ MAX1621 include a 5-bit DAC, allowing digital software control of the bias voltage. The MAX1620 uses up/down digital signaling to adjust the DAC, and the MAX1621 uses the System Management Bus (SMBusTM) 2-wire serial interface. These devices use a low-cost, external, N-channel MOSFET power switch or NPN transistor, and can be configured for positive or negative output voltages. Operating current is a low 150A, typically provided from a display's logic supply of 3.0V to 5.5V. The MAX1620/MAX1621 are available in a 16-pin QSOP package. o 1.8V to 20V Battery Input Voltage o Automatic Disable when Display Logic is Shut Down o Extremely Small QSOP Package o 32-Level Internal DAC o SMBus Serial Interface (MAX1621) o Positive or Negative Output Voltage
Features
MAX1620/MAX1621
Ordering Information
PART MAX1620EEE MAX1621EEE TEMP. RANGE -40C to +85C -40C to +85C PIN-PACKAGE 16 QSOP 16 QSOP
Applications
Notebook Computers Palmtop Computers Personal Digital Assistants Portable Data-Collection Terminals
Typical Operating Circuit
2V TO 12V
Pin Configuration
TOP VIEW
DN (SDA) 1 UP (SCL) 2 BATT 3 SHDN (SUS) 4 POK 5 REF 6 POL 7 LCDON 8 16 DHI 15 DLO 14 LX ON/OFF DOWN UP 3V TO 5.5V VDD POL
BATT LX DHI DLO PGND
12.5V TO 23.5V OUT
SHDN DN UP
MAX1620 MAX1621
13 PGND 12 AGND 11 VDD 10 DOUT 9 FB
MAX1620
REF AGND POK DOUT FB LCDON
( ) ARE FOR MAX1621 ONLY.
QSOP
SMBus is a trademark of Intel Corp.
________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769.
Digitally Adjustable LCD Bias Supplies MAX1620/MAX1621
ABSOLUTE MAXIMUM RATINGS
VDD to AGND ..............................................................-0.3V to 6V PGND to AGND ..................................................................0.3V BATT, LX, LCDON to AGND ....................................-0.3V to 30V DHI, DLO to PGND.....................................-0.3V to (VDD + 0.3V) DOUT, FB, POL, POK, REF to AGND.........-0.3V to (VDD + 0.3V) UP, DN, SHDN to AGND.............................................-0.3V to 6V SCL, SDA, SUS to AGND............................................-0.3V to 6V IDHI ......................................................................................60mA IDLO....................................................................................-30mA I LCDON ...............................................................................-10mA Continuous Power Dissipation (TA = +70C) QSOP (derate 8.3mW/C above +70C) ......................667mW Operating Temperature Range MAX1620EEE/MAX1621EEE ............................-40C to +85C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 3.3V, VBATT = 10V, TA = 0C to +85C, unless otherwise noted.) PARAMETER SWITCHING REGULATOR VDD Operating Range VDD Supply Current Positive Output Voltage Negative Output Voltage Undervoltage Lockout Threshold (Note 1) BATT Input Current LX Input Current BATT Operating Range (Note 2) Microsecond-Volt Time Constant (k-factor) On-Resistance (DLO, DHI) DHI Output Current (Note 3) DLO Output Current (Note 3) FB Regulation Voltage FB Input Current (Note 3) LCDON Low, Sinking Current LCDON High, Leakage Current POK Threshold Voltage POK Hysteresis REFERENCE AND DAC OUTPUT REF Voltage REF Load Regulation 2 No load 0A IREF 25mA 1.47 1.5 3 1.53 10 V mV 1.8V BATT 20V, TA = +25C 4V BATT 12V, TA = 0C to +85C VDD = 4.5V VDD = 3.0V VDD = 5V VDD = 5V POL = VDD, 3.0V VDD 5.5V POL = AGND, 3.0V VDD 5.5V FB = REF + 100mV FB = -50mV V LCDON = 0.4V, POK = 1.017V V LCDON = 28V, POK = 0.967V Voltage on POK rising 0.967 0.992 12 1.46 -8 -20 -10 -2 -6 1 1.017 16.5 7 14 50 -25 1.5 0 1.53 8 10 85 BATT = 12V, operating mode BATT = 12V, shutdown mode LX = 12V, operating mode LX = 12V, shutdown mode 1.8 20 23.5 13 1.5 13 Operating mode, output in regulation, VDD = 5.5V Shutdown mode, V SHDN = VDD, VDD = 5.5V 3.0 150 9 5.5 250 20 27 -27 2.8 20 1 20 V A V V V A A V s-V mA mA V mV nA mA A V mV CONDITIONS MIN TYP MAX UNITS
1
20
_______________________________________________________________________________________
Digitally Adjustable LCD Bias Supplies
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, VBATT = 10V, TA = 0C to +85C, unless otherwise noted.) PARAMETER DOUT Maximum Output Voltage (Note 3) DOUT Minimum Output Voltage (Note 3) DOUT Resolution DOUT Differential Nonlinearity DIGITAL INPUTS AND OUTPUTS UP, DN, SHDN, POL Input High Voltage UP, DN, SHDN, POL Input Low Voltage UP, DN, SHDN, POL Input Leakage Current SCL, SDA, SUS Input High Voltage SCL, SDA, SUS Input Low Voltage SCL, SDA, SUS Input Leakage Current SDA Output Low Voltage VIN = 0V or VIN = VDD ISDA = -6mA VIN = 0V or VIN = VDD 3.0V VDD 3.6V VDD = 5.5V 1.4 2.3 0.6 1 0.4 3.0V VDD 3.6V VDD = 5.5V 1.4 2.3 0.6 1 V V A V V A V CONDITIONS 0A IDOUT 40A -20A IDOUT 0A 48.39mV step size Guaranteed monotonic MIN REF 0.02 0 5 1 TYP MAX REF + 0.02 0.007 UNITS V V Bits LSB
MAX1620/MAX1621
TIMING CHARACTERISTICS
(TA = 0C to +85C, unless otherwise noted.) PARAMETER MAX1620 (Figure 1) Pulse Width High (UP, DN) Pulse Width Low (UP, DN) Pulse Separation (UP, DN) Counter Reset Time MAX1621 (Figures 2 and 3) SDA to SCL Data-Setup Time SCL to SDA Data-Hold Time SCL/SDA Rise Time SCL/SDA Fall Time SCL Low Time SCL High Time Start Condition SCL to SDA Setup Time Start Condition SDA to SCL Hold Time Stop Condition SCL_ to SDA_ Setup Time SCL Falling Edge to SDA Valid Master Clocking in Data tSU:DAT tHD:DAT tR tF tLOW tHIGH tSU:STA tHD:STA tSU:STO tDV (Note 4) (Note 4) (Note 4) 4.7 4 4.7 4 4 1 500 0 1 300 ns ns s ns s s s s s s t1 t2 t3 t4 1 1 1 1 s s s s SYMBOL CONDITIONS MIN TYP MAX UNITS
_______________________________________________________________________________________
3
Digitally Adjustable LCD Bias Supplies MAX1620/MAX1621
ELECTRICAL CHARACTERISTICS
(VDD = 3.3V, VBATT = 10V, TA = -40C to +85C. Typical values are at TA = +25C, unless otherwise noted. Limits over this temperature range are guaranteed by design.) PARAMETER SWITCHING REGULATOR VDD Operating Range VDD Supply Current Positive Output Voltage Negative Output Voltage Undervoltage Lockout Threshold (Note 1) BATT Operating Range (Note 2) Microsecond-Volt Time Constant (k-factor) FB Regulation Voltage FB Input Current (Note 3) POK Threshold Voltage REFERENCE AND OUTPUT REF Voltage REF Load Regulation DOUT Maximum Output Voltage (Note 3) DOUT Minimum Output Voltage (Note 3) DOUT Differential Nonlinearity DIGITAL INPUTS AND OUTPUTS UP, DN, SHDN, POL Input High Voltage UP, DN, SHDN, POL Input Low Voltage SCL, SDA, SUS Input High Voltage SCL, SDA, SUS Input Low Voltage SDA Output Low Voltage ISDA = -6mA 3.0V VDD 3.6V VDD = 5.5V 1.4 2.3 0.6 0.4 3.0V VDD 3.6V VDD = 5.5V 1.4 2.3 0.6 V V V V V No load 0A IREF 25A 0A IDOUT 40A -20A IDOUT 0A Guaranteed monotonic REF 0.02 0 1.44 1.5 5 1.56 10 REF + 0.02 0.01
1
CONDITIONS
MIN 3.0
TYP
MAX 5.5
UNITS V A V V V V s-V V mV nA V V mV V V LSB
Operating mode, output in regulation Shutdown mode, VSHDN = VDD
150
250 20 27 -27
1.5 1.8 4V BATT 12V POL = VDD, 3.0V VDD 5.5V POL = AGND, 3.0V VDD 5.5V FB = REF + 100mV FB = 0V - 50mV Voltage on POK rising 16 1.44 -10 -30 -10 0.957 0.992 1.5 0
2.8 20 24 1.56 10 10 120 1.027
4
_______________________________________________________________________________________
Digitally Adjustable LCD Bias Supplies
TIMING CHARACTERISTICS
(VDD = 3.3V, VBATT = 10V, TA = -40C to +85C. Typical values are at TA = +25C, unless otherwise noted. Limits over this temperature range are guaranteed by design.) PARAMETER MAX1620 (Figure 1) Pulse Width High (UP, DN) Pulse Width Low (UP, DN) Pulse Separation (UP, DN) Counter Reset Time MAX1621 (Figures 2 and 3) SDA_ to SCL_ Data-Setup Time SCL_ to SDA_ Data-Hold Time SCL/SDA Rise Time SCL/SDA Fall Time SCL Low Time SCL High Time Start Condition SCL_ to SDA_ Setup Time Start Condition SDA_ to SCL_ Hold Time Stop Condition SCL_ to SDA_ Setup Time SCL Falling Time to SDA Valid Master Clocking in Data Note 1: Note 2: Note 3: Note 4: tSU:DAT tHD:DAT tR tF tLOW tHIGH tSU:STA tHD:STA tSU:STO tDV 4.7 4 4.7 4 4 1 500 0 1 300 ns ns s ns s s s s s s t1 t2 t3 t4 1 1 1 1 s s s s SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX1620/MAX1621
The setting in the DAC is guaranteed to remain valid as long as VDD is greater than the UVLO threshold. BATT Operating Range is guaranteed by the Microsecond-Volt Time Constant specification. Current sourced from a pin is denoted as positive current. Current sunk into a pin is denoted as negative current. Guaranteed by design.
__________________________________________Typical Operating Characteristics
(VDD = 5V, VBATT = 10V, L1 = 100H, TA = +25C, unless otherwise noted.)
EFFICIENCY vs. OUTPUT CURRENT
MAX1620/21-01
EFFICIENCY vs. OUTPUT CURRENT
MAX1620/21-02
EFFICIENCY vs. OUTPUT VOLTAGE
MAX1620/21-03
1.00 0.95 EFFICIENCY (%) 0.90 +25V 0.85 0.80 0.75 0.70 0 10 20 30 40 50 60
1.00 0.95 EFFICIENCY (%) 0.90 -25V 0.85 0.80 0.75 0.70 -15V
1.00 0.95 +20mA EFFICIENCY (%) 0.90 0.85 0.80 0.75 0.70 +10mA
+15V
70
0
10
20
30
40
50
60
70
12
14
16
18
20
22
24
26
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
OUTPUT VOLTAGE (V)
_______________________________________________________________________________________
5
Digitally Adjustable LCD Bias Supplies MAX1620/MAX1621
_____________________________Typical Operating Characteristics (continued)
(VDD = 5V, VBATT = 10V, L1 = 100H, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX1620/21-05
EFFICIENCY vs. OUTPUT VOLTAGE
MAX1620/21-04
EFFICIENCY vs. VBATT
1.00 0.95 EFFICIENCY (%) 0.90 0.85 0.80 0.75 0.70 +20V, +10mA -20V, -10mA 200 180 160 SUPPLY CURRENT (A) 140 120 100 80 60 40 20
0.95 EFFICIENCY (%) 0.90 0.85 0.80 0.75 0.70 -26 -24 -22 -20 -18 -16 -14
-20mA -10mA
0 2 4 6 8 10 12 14 16 18 20 0 1 2 3 4 5 VBATT (V) SUPPLY VOLTAGE (V)
-12
OUTPUT VOLTAGE (V)
SUPPLY CURRENT vs. TEMPERATURE
MAX1620/21-07
SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX1620/21-08
SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE
MAX1620/21-09
200
20 18 16 SUPPLY CURRENT (A) 14 12 10 8 6 4 2
20 18 SUPPLY CURRENT (A) 16 14 12 10 8 6
SUPPLY CURRENT (A)
175
150
125
100 -40 -20 0 20 40 60 80 TEMPERATURE (C)
0 0 1 2 3 4 5 SUPPLY VOLTAGE (V)
-40
-20
0
20
40
60
80
TEMPERATURE (C)
REFERENCE VOLTAGE vs. TEMPERATURE
MAX1620/21-10
k-FACTOR vs. SUPPLY VOLTAGE
MAX1620/21-11
k-FACTOR vs. TEMPERATURE
21.5 21.0 k-FACTOR (s-V) 20.5 20.0 19.5 19.0 18.5 18.0
MAX1620/21-12
1.51
22.0 21.5 21.0 k-FACTOR (s-V) 20.5 20.0 19.5 19.0 18.5
22.0
REFERENCE VOLTAGE (V)
1.50
1.49 -40 -20 0 20 40 60 80 TEMPERATURE (C)
18.0 2.5 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V)
-60 -40
-20
0
20
40
60
80
100
TEMPERATURE (C)
6
_______________________________________________________________________________________
MAX1620/21-06
1.00
Digitally Adjustable LCD Bias Supplies
_____________________________Typical Operating Characteristics (continued)
(VDD = 5V, VBATT = 10V L1 = 100H, VOUT = 22.3V, TA = +25C, unless otherwise noted.)
k-FACTOR vs. VBATT
24 23 k-FACTOR (s-V) 22 21 20 19 18 17 16 15 0 5 10 VBATT (V) 15 20
MAX1620/21-13
MAX1620/MAX1621
25
LINE-TRANSIENT RESPONSE
MAX1620/21-14
LOAD-TRANSIENT RESPONSE
MAX1620/21-15
VOUT (AC COUPLED, 5mV/div)
VOUT (AC COUPLED, 20mV/div)
5.3V VDD (AC COUPLED, 1V/div) 3.3V 2ms/div ILOAD = 20mA ILOAD = 0mA TO 20mA 2ms/div
20mA IOUT (10mA/div) 0
_______________________________________________________________________________________
7
Digitally Adjustable LCD Bias Supplies
______________________________________________________________Pin Description
MAX1620/MAX1621
PIN NAME MAX1620 1 -- 2 -- 3 4 -- 5 6 7 8 9 10 11 12 13 14 15 16 MAX1621 -- 1 -- 2 3 -- 4 5 6 7 8 9 10 11 12 13 14 15 16 DN SDA UP SCL BATT SHDN SUS POK REF POL LCDON FB DOUT VDD AGND PGND LX DLO DHI Logic-Level Input. A rising edge on DN decreases VOUT. UP = DN = high resets the counter to mid-scale. System Management Bus Serial-Data Input and Open-Drain Output Logic-Level Input. A rising edge on UP increases VOUT. UP = DN = high resets the counter to mid-scale. System Management Bus Serial-Clock Input Battery Voltage-Sense Input Logic-Level Shutdown Input (active-low) System Management Bus Suspend-Mode Input (active-low) Power OK Voltage-Sense Input, 1V threshold Reference Voltage Output. Bypass REF with 0.1F to AGND. Logic-Level Input. POL selects output voltage polarity: high = positive boost, low = negative boost. Open-Drain Output. LCDON controls LCD with external PNP. Feedback Voltage Input DAC Output Voltage IC Input Supply, 3.0V to 5.5V Analog Ground Power Ground Switching-Voltage Sense Input External Transistor Drive, Low External Transistor Drive, High FUNCTION
8
_______________________________________________________________________________________
Digitally Adjustable LCD Bias Supplies MAX1620/MAX1621
t1 t2 t4
UP t3
DN
Figure 1. MAX1620 UP and DN Signal Timing
START CONDITION MOST SIGNIFICANT ADDRESS BIT (A6) CLOCKED INTO SLAVE A5 CLOCKED INTO SLAVE A4 CLOCKED INTO SLAVE A3 CLOCKED INTO SLAVE
SCL
tHD:STA
tLOW
tHIGH tSU:STO
SDA
tSU:STA
tSU:DAT
tHD:DAT
tSU:DAT
tHD:DAT
Figure 2. MAX1621 SMB Serial-Interface Timing--Address
RW BIT CLOCKED INTO SLAVE ACKNOWLEDGED BIT CLOCK INTO MASTER
MOST SIGNIFICANT BIT CLOCKED
SCL
***
SLAVE PULLING SDA LOW
SDA
***
tDV tDV
Figure 3. MAX1621 SMB Serial-Interface Timing--Acknowledge
_______________________________________________________________________________________ 9
Digitally Adjustable LCD Bias Supplies MAX1620/MAX1621
_______________Detailed Description
The MAX1620/MAX1621 are step-up power controllers that drive an external N-channel FET or NPN transistor to convert power from a 1.8V to 20V battery to a higher positive or negative voltage. They are configured as negative-output, inverting power controllers with one additional diode and one additional capacitor. Either configuration's output voltage can be adjusted with external resistors, or digitally adjusted with an internal digital-to-analog converter (DAC). The MAX1620 uses pin-defined controls for the DAC, while the MAX1621 communicates with the DAC via the SMBusTM interface. Discontinuous conduction is detected by monitoring the LX node voltage. When the inductor's energy is completely delivered, the LX node voltage snaps back to the BATT voltage. When this crossing is sensed, another pulse is issued if the output is still out of regulation.
Positive Output Voltage
To select a positive output voltage, tie the polarity pin (POL) to VDD and use the typical boost topology shown in Figure 4. FB regulation voltage is 1.5V. For optimum stability, VOUT should be greater than 1.1 (VBATT).
Negative Output Voltage
To select a negative output voltage, tie POL to GND (Figure 5). In this configuration, the internal error amplifier's output is inverted to provide the correct feedback polarity. FB regulation voltage is 0V. D1, D2, C4, and C5 form an inverting charge pump to generate the negative voltage. This allows application of the positive boost switching topology to negative output voltages. The negative output circuit has two possible connections. In the standard connection, D1's cathode is connected to BATT. This connection features the best output ripple performance, but VOUT must be limited to no more than 27V - 1.1(VBATT). If a larger negative voltage is needed, an alternative connection allows a maximum negative output of -27V, but with the additional constraint that VOUT > 1.1VBATT. To use the alternative circuit, connect D1's cathode to ground rather than BATT (Figure 6). Increase C4 to 2.2F to improve output ripple performance. The negative charge pump limits the output current to the charge transferred each cycle multiplied by the
Operating Principle
The MAX1620/MAX1621 operate in discontinuousconduction mode (where the inductor current ramps to zero by the end of each switching cycle) and with a constant peak current, without requiring a currentsense resistor. Switch on-time is inversely proportional to the input voltage VBATT by a microsecond-volt constant, or k-factor, of 20s-V (e.g., for V BATT = 10V, on-time = 2s). For an ideal boost converter operating in discontinuous-conduction mode (no power losses), output current is proportional to input voltage and peak inductor current:
1 x IPK x VBATT / VOUT 2 IPK is proportional to on-time (tON), which, for these parts, is determined by the k-factor: IOUT =
IPK = k-factor / L
2V TO 12V OPTIONAL
R1 360k
R8 10k D3 1N6263 (ANY SCHOTTKY) TO REF 3 5 11 7 4 1 2 6 12
C3 22F
L1 100H 12.5V TO 23.5V OUT Q1 MMBT2907 R7 56k VOUTSW R4 300k C6 100pF
R2 100k
3V TO 5.5V
C1 0.1F
C2 0.1F
U1 BATT LX POK DHI VDD DLO MAX1620 MAX1621 PGND POL SHDN (SUS) DN (SDA) DOUT UP (SCL) FB REF AGND LCDON
( ) ARE FOR MAX1621.
14 16 15 13 10 9 8 R3 300k
D1 MBRS0540 N1 MMFT3055VL R5 2.2M
C5 22F
R6 56k
NOTE: CONNECTIONS TO DIGITAL INPUTS NOT SHOWN.
OPTIONAL
Figure 4. Typical Operating Circuit--Positive Output
10 ______________________________________________________________________________________
Digitally Adjustable LCD Bias Supplies MAX1620/MAX1621
2V TO 15V
R8 10k D3 1N6263 (ANY SCHOTTKY) TO REF 3 5 11 7 4 1 2 6 12
C3 22F
L1 100H
D1 MBRS0540 -6V TO -12V OUT
3V TO 5.5V
C1 0.1F
C2 0.1F
U1 BATT POK VDD MAX1620 MAX1621 POL SHDN (SUS) DN (SDA) UP (SCL) REF AGND
LX DHI DLO PGND DOUT FB LCDON
14 16 15 13 10 9 8
C4 1F N1 MMFT3055VL R3 300k
D2 MBRS0540
C5 22F
R5 1.2M
( ) ARE FOR MAX1621.
R4 300k C6 100pF
NOTE: CONNECTIONS TO DIGITAL INPUTS NOT SHOWN.
Figure 5. Typical Operating Circuit--Negative Output
2V TO 12V
R8 10k D3 1N6263 (ANY SCHOTTKY) TO REF 3 5 11 7 4 1 2 6 12
C3 22F
L1 100H
D2 MBRS0540 C5 22F -13.5V TO -27V OUT
3V TO 5.5V
C1 0.1F
C2 0.1F
U1 BATT POK VDD MAX1620 MAX1621 POL SHDN (SUS) DN (SDA) UP (SCL) REF AGND
LX DHI DLO PGND DOUT FB LCDON
14 16 15 13 10 9 8
C4 2.2F N1 MMFT3055VL R3 300k
D1 MBRS0540
R5 2.7M
( ) ARE FOR MAX1621.
R4 300k C6 100pF
NOTE: CONNECTIONS TO DIGITAL INPUTS NOT SHOWN.
Figure 6. Alternative Negative Output--Maximum Voltage
maximum switching frequency. The following equation represents the output current for the ideal case (no power losses) of Figure 5: 1 IOUT = x (k - factor / L) x VBATT / (VBATT + VOUT ) 2 This means that a higher peak current is required to achieve the same output current in the negative output circuit as in the positive output circuit. The output current for Figure 6 uses the same current equation as the positive boost.
Output Voltage Control
The output voltage is set with a voltage divider to the feedback pin (FB). For a positive output, the divider is referred to GND; for a negative output, the divider is referred to REF. Output voltage can be adjusted with an internal DAC summing current into FB through an external resistor. The 5-bit DAC is controlled with a user-programmable up/down counter. On power-up or after a reset, the counter sets the DAC output to 10000 binary, or halfscale.
11
______________________________________________________________________________________
Digitally Adjustable LCD Bias Supplies MAX1620/MAX1621
The MAX1620 controls the DAC counter with the UP and DN pins. A rising edge on UP increases VOUT by decrementing the counter and decreasing the DAC output voltage one step; a rising edge on DN decreases V OUT by incrementing the counter and increasing the DAC output voltage one step. Holding both UP and DN high resets the counter to half-scale. The counter will not roll over at either the FS or ZERO code. The control direction of UP and DN reverses for a negative output, to maintain the same control direction of the output voltage in absolute magnitude. The MAX1621 controls the counter to the DAC through the SMBus interface. The counter is treated as a 5-bit register and resets on power-up. The setting in the DAC is guaranteed to remain valid as long as VDD is greater than the UVLO threshold (see Note 1 in the Electrical Characteristics). The MAX1620/MAX1621's open-drain DMOSFET (LCDON) can be used to disconnect the LCD panel from the positive bias voltage with an external transistor. The FET turns off (LCDON = float) if power-OK voltage (POK) falls below 1V. In the MAX1621, LCDON can also be controlled by the SMB command. LCDON cannot switch negative output voltages. To prevent uncontrolled boosting when the output is disconnected, the feedback resistors must sense the boosted voltage rather than the output of the LCDON switch (Figure 4). The MAX1620/MAX1621 reset the DAC counter to midscale at power-up or when VDD is below the undervoltage lockout threshold of 2.2V (typ).
MAX1621 Digital Interface
A single byte of data written over the Intel SMBus controls the MAX1621. Figures 7 and 8 show example single-byte writes. The MAX1621 contains two 2-bit registers for storing configuration data, and one register for the 5-bit DAC data. Tables 1 and 2 describe the data format for the configuration registers. The MAX1621 responds only to its own address (0101100 binary). The REGSEL bit addresses the configuration registers. REGSEL = 0 for the SUS register; REGSEL = 1 for the OPR register. Each configuration register consists of a SHDN bit and an LCDON bit. One of the two configuration registers is always active. The state of the SUS pin determines the active register. The OPR register is active with SUS = high. The SUS register is active with SUS = low. Each byte written to the MAX1621 updates the DAC register. DAC data is preserved in shutdown and when toggling between configuration registers. Since there is only one DAC register, SUS cannot be used to toggle between two DAC codes. Status information can be read from the MAX1621 using the SMBus read-byte protocol. Figure 9 shows an example status read and Table 3 describes the statusinformation format. During shutdown (SUS = 1 and OPR-SHDN = 0, or SUS = 0 and SUS-SHDN = 0), the MAX1621 serial interface remains fully functional and can be used to set either the OPR-SHDN or SUS-SHDN bits to return the MAX1621 to its normal operational state.
Shutdown Mode
The MAX1620 shuts down when the SHDN pin is low. The internal reference and biasing circuitry turn off, and the supply current drops to 9A. In shutdown, DOUT = 0V and LCDON floats. UP/DN are ignored to preserve the DAC state for the MAX1620. Tie unused logic inputs to AGND for lowest operating current. The MAX1621 can be shut down using the SMBus interface (Table 2).
Reset Modes
If the MAX1620 is not in shutdown mode, the DAC can be reset to mid-scale by holding UP and DN high. Midscale is 16 steps from the minimum DAC output and 15 steps from the maximum.
Separate/Same Power for L1 and VDD Separate voltage sources can supply the inductor (L1) and the IC (VDD). This allows operation from low-voltage batteries as well as high-voltage sources because chip bias (150A) is provided by a logic supply (3V to 5.5V) while output power is sourced directly from the battery to L1. Conversely, L1 and VDD can also be supplied from one supply if it remains with VDD's operating limits (3V to 5.5V). If L1 and VDD are fed from the same voltage, D3 and R8 (Figures 4, 5, 6, and 10) can be omitted, and BATT may be connected directly to VDD.
12
______________________________________________________________________________________
Digitally Adjustable LCD Bias Supplies MAX1620/MAX1621
Table 1. MAX1621 Configuration Byte with REGSEL = 0 (write to SUS register)
BIT NAME POR STATE* DESCRIPTION Register Select. A zero in this bit writes the next two bits into the SUS register and the remaining five bits into the DAC register (Figure 7). With SUS = low, 1 = operating, and 0 = shutdown. With SUS = low, 1 = LCD on, and 0 = LCD off.
Table 2. MAX1621 Configuration Byte with REGSEL = 1 (write to OPR register)
BIT NAME POR STATE* DESCRIPTION Register Select. A one in this bit writes the next two bits into the OPR register and the remaining five bits into the DAC register (Figure 7). With SUS = high, 1 = operating, and 0 = shutdown. With SUS = high, 1 = LCD on, and 0 = LCD off.
7
REGSEL
--
7
REGSEL
--
6
SUS-SHDN
0
6
OPR-SHDN
1
5 4 3 2 1 0
SUS-LCDON D4 (MSB) D3 D2 D1 D0
0 1 0 0 0 0
5 4 3 2 1 0
OPR-LCDON D4 (MSB) D3 D2 D1 D0
1 1 0 0 0 0
DAC Input Data
DAC Input Data
*Initial register state after power-up.
*Initial register state after power-up.
Table 3. MAX1621 Status Bits
BIT NAME DESCRIPTION If the voltage applied to POK is greater than 0.992V and the MAX1621 is not shut down, this bit returns 1; otherwise, it returns 0. Reserved for future use. Reserved for future use.
7
POK
6 5 4 3 2 1 0
-- -- D4 (MSB) D3 D2 D1 D0
DAC Register Data
______________________________________________________________________________________
13
Digitally Adjustable LCD Bias Supplies MAX1620/MAX1621
MOST SIGNIFICANT ADDRESS BIT START CONDITION
LEAST SIGNIFICANT ADDRESS BIT
SLAVE ACKNOWLEDGE MOST SIGNIFICANT R/W BIT DATA BIT
SLAVE ACKNOWLEDGE LEAST SIGNIFICANT DATA BIT
SCL SUS-SHDN SDA REGSEL SLAVE PULLS SDA LOW SUS-LCDON D4 D3 DAC DATA D2 D1 D0 SLAVE PULLS SDA LOW
Figure 7. MAX1621 Serial-Interface Single-Byte Write Example (REGSEL = 0)
MOST SIGNIFICANT ADDRESS BIT START CONDITION
LEAST SIGNIFICANT ADDRESS BIT
SLAVE ACKNOWLEDGE MOST SIGNIFICANT R/W BIT DATA BIT
SLAVE ACKNOWLEDGE LEAST SIGNIFICANT DATA BIT
SCL OPR-SHDN SDA SLAVE PULLS SDA LOW REGSEL OPR-LCDON D4 D3 DAC DATA D2 D1 D0 SLAVE PULLS SDA LOW
Figure 8. MAX1621 Serial-Interface Single-Byte Write Example (REGSEL = 1)
14
______________________________________________________________________________________
Digitally Adjustable LCD Bias Supplies MAX1620/MAX1621
MOST SIGNIFICANT ADDRESS BIT START CONDITION
LEAST SIGNIFICANT ADDRESS BIT
SLAVE ACKNOWLEDGE MOST SIGNIFICANT R/W BIT DATA BIT
SCL
SDA SLAVE PULLS SDA LOW
POK
D4
D3
D2
D1
D0
MAX1621 DRIVES SDA
Figure 9. MAX1621 Serial-Interface Read Example
Design Procedure __________and Component Selection
The MAX1620/MAX1621 output voltage can be adjusted manually or via a digital interface. In addition, positive bias voltage can be switched with LCDON using an external PFET or PNP transistor.
For example, if VOUT,MIN = 12.5V: R5 = 300k x (12.5 - 1.5) / (1.5) = 2.2M Mount R4 and R5 close to the FB pin to minimize parasitic capacitance. For a negative output voltage, the FB threshold voltage is 0V, and R4 is placed between FB and REF (Figures 5 and 6). Again, choose R4 to be 300k so that the current in the divider is about 5A. Then determine R5 as follows: R5 = R4 x VOUT,MIN / VREF For example, if VOUT,MIN = -12.5V:
Output Adjustment
Setting the Minimum Output Voltage The minimum output voltage is set with a resistor-divider (R4-R5, Figure 4) from VOUT to AGND. The FB threshold voltage is 1.5V. Choose R4 to be 300k so that the current in the divider is about 5A. Determine R5 as follows:
R5 = R4 x (VOUT,MIN - VFB) / VFB
R5 = 300k x (12.5) / (1.5) = 2.5M
______________________________________________________________________________________
15
Digitally Adjustable LCD Bias Supplies MAX1620/MAX1621
Setting the Maximum Output Voltage (DAC Adjustment) The DAC is adjustable from 0V to 1.5V in 32 steps, and 1LSB = 1.5V / 31. DAC adjustment of VOUT is provided by adding R3 to the divider circuit (Figure 4). Be sure that VOUT,MAX does not exceed the LCD panel rating. For VOUT,MAX = 25V and VOUT,MIN = 12.5V, R3 is determined as follows:
R3 = R5 x (VFB) / (VOUT,MAX - VOUT,MIN) = 2.2M x (1.5) / (25 - 12.5) = 264k The general form for VOUT as a function of the DAC output (VDOUT) is: VOUT = VOUT,MIN + (VFB - VDOUT) x R5 / R3 At power-up the DAC resets to mid-scale (10000), which corresponds to VDOUT = 0.774V; therefore, the output voltage after reset is as follows: VOUT,RESET = VOUT,MIN + (1.5 - 0.774) x R5 / R3 Note that for a positive output voltage, VOUT increases as VDOUT decreases. VOUT,MAX corresponds to VDOUT = 0V, and VOUT,MIN corresponds to VDOUT = 1.5V. For a negative output voltage, VOUT = V OUT,MIN + (VFB - VDOUT) x R5 / R3. Assume VOUT,MAX = -25V and VOUT,MIN = -12.5V; then determine R3 and VOUT,RESET as follows: R3 = R5 x (VFB - VDOUT,MAX) / (VOUT,MAX - VOUT,MIN) = 2.5M x (0 - 1.5) / (-25 - -12.5) = 300k VOUT,RESET = -12.5 + (0 - 0.774) x (2.5M) / (300k) = -18.95V Note that for a negative output voltage, VOUT increases as VDOUT increases. VOUT,MAX corresponds to VDOUT = 1.5V, and VOUT,MIN corresponds to VDOUT = 0V.
Controlling the LCD Using POK and LCDON
When voltage at POK is greater than 1V, the open-drain LCDON output pulls low. LCDON withstands 27V; therefore, it can drive a PFET or PNP transistor to switch on the MAX1620/MAX1621's positive output. The following represent three cases for using this feature: 1) As an off switch, to ensure that a positive boosted output goes to 0V during shutdown. In this case, connect POK to SHDN. Without this switch, the positive output falls to one diode-drop below the input voltage (VBATT) in shutdown. LCDON is not needed for negative outputs, which will fall to 0V in shutdown anyway. 2) As an output sensing cutoff for positive outputs. Connect POK to the feedback voltage divider to sense the output voltage. The output is switched on only when it reaches a set percentage of the set voltage. 3) As an input sensing output cutoff for positive outputs. Connect POK to a voltage divider to sense the input voltage. The output is switched on only when the input reaches the set level (Figure 4). To control the open-drain output LCDON by sensing the input voltage, connect a resistor-divider (R1-R2, Figure 4) from VBATT to POK. Choose R2 = 100k. For example, if the minimum battery voltage is 5.3V, determine R1 as follows: R1 = R2 x [(VBATT / VPOK) - 1] = 100k x [(5.3 / 0.992) - 1] = 434k LCDON can also be controlled via software (MAX1621, Table 4).
Table 4. MAX1621 LCDON Output Truth Table
POK Pin <1V <1V >1V >1V LCDON Bit 0 1 0 1 LCDON Output Floating Floating Floating ON, pulls low
Potentiometer Adjustment The output can be adjusted with a potentiometer instead of the DAC. Choose R POT = 100k, and connect it between REF and GND. Connect R3 to the potentiometer's wiper, instead of to DOUT. The same design equations as above apply.
16
______________________________________________________________________________________
Digitally Adjustable LCD Bias Supplies
LCDON typically drives an external PNP transistor, switching a positive VOUT to the LCD. R7 limits the base current in the PNP; R6 turns off the PNP when LCDON is floating. R6 and R7 can be the same value. Choose R7 such that the minimum base current is greater than 1/50 of the collector current. For example, assume VOUT,MIN = 12.5V and ILCD = 10mA, then determine R7 as follows: R7 50 x (12.5 - 0.7) / 10mA = 59k Remember that LCD voltage is the regulated output voltage minus the drop across the PNP switch. The drop across the external transistor (typically 300mV) must be accounted for. If a PFET is preferred for the LCDON switch, R6 and R7 in Figure 4 may both be raised to 1M or more to reduce operating current. Be sure to choose a PFET with adequate breakdown voltage. Since load current is typically on the order of 10mA, an on-resistance of 10 or less is usually adequate. coil inductance; however, for most inductor types, the coil's specified current can be exceeded by 20% with no impact on efficiency. The peak current is set by the coil inductance as follows: IPK = k-factor / L and
MAX1620/MAX1621
IOUT,MIN =
1 x IPK x VBATT,MIN / VOUT,MAX 2
If we assume that V BATT,MIN = 5.3V, V OUT,MAX = 25V, I OUT,MIN = 15mA, and a minimum k-factor of 16s-V, then the required IPK is: IPK = 2 x 15mA x 25 / 5.3 = 142mA and L = 16s-V / 142mA = 113H
The next-lowest practical inductor value is 100H. Its current rating must be: 24s-V (maximum k-factor) / 100H = 240mA Table 5 summarizes the minimum inductance value needed to provide various output currents at several minimum input voltages. Table 6 lists some suitable coil types and manufacturers, but is not intended to be a complete list.
Choosing an Inductor
Practical inductor values range from 33H to 1mH; however, 100H is a good choice for a wide range of applications. Inductors with a ferrite core or equivalent are recommended. The inductor's current rating should exceed the peak current as set by the k-factor and the
Table 5. Maximum Inductance vs. IOUT and VBATT,MIN (20V output)
VBATT,MIN 1.8V 5mA 10mA IOUT 20mA 30mA 27H 18H 39H 27H 56H 33H 82H 56H 100H 68H 180H 120H 100H 56H 2.7V 150H 82H 3.6V 220H 100H 5.4V 330H 150H 7.2V 390H 220H 12V 680H 330H
Table 6. Inductor List
COMPANY Sumida USA (847) 956-0666 Japan 81-3-3607-5111 Coilcraft (847) 639-6400 TDK (847) 390-4373 PART CD43 CD54 CDRH62B DO1608 DT1608 NLC565050 TPF0410 H RANGE Up to 68H Up to 220H Up to 330H Up to 1mH Up to 400H Up to 1mH Up to 1mH SIZE IN mm (H x W x L) 3.2 x 4 diameter 4.5 x 5.2 diameter 3 x 6.2 x 6.2 3.18 x 4.45 x 6.6 3.18 x 4.45 x 6.6 5 x 5 x 5.6 4 diameter x 10 L Leaded coil 17 Shielded Shielded COMMENTS
______________________________________________________________________________________
Digitally Adjustable LCD Bias Supplies MAX1620/MAX1621
Diode Selection
The high maximum switching frequency of 300kHz requires a high-speed rectifier. Schottky diodes, such as the MBRS0540, are recommended. To maintain high efficiency, the average current rating of the Schottky diode must be greater than the peak switching current. Choose a reverse breakdown voltage greater than the positive output voltage or greater than the negative output voltage plus VBATT.
Input Bypass Capacitor
Two inputs, VDD and VBATT, require bypass capacitors. Bypass VDD with a 0.1F ceramic capacitor as close to the IC as possible. The battery supplies high currents to the inductor and requires local bulk bypassing close to the inductor. A 22F low-ESR surface-mount capacitor is sufficient for most applications. Smaller capacitors are acceptable if peak inductor current is low or the battery's internal impedance is low and the battery is close to the inductor.
External Switching Transistor
Again, the high maximum switching frequency requires a high-speed switching transistor to maintain efficiency. Logic-level N-channel MOSFETs, such as the MMFT3055VL, are recommended (N1). Choose a VDS rating greater than the positive output voltage or greater than the negative output voltage plus VBATT. To save cost in certain applications, a bipolar transistor may be substituted for the MOSFET with a decrease in efficiency. The conditions favoring substitution are limited input voltage range (VDD), low maximum battery voltage (VBATT), and low output current. For example, VDD = 3.0V to 3.6V, VBATT,MAX = 12V, and IOUT = 5mA favors a bipolar transistor substitution to reduce cost. To modify the Typical Operating Circuit (Figures 4 and 5) for a bipolar switching transistor, connect the collector to the inductor, the base to DLO, and the emitter to PGND (Figure 10). Connect the base to DHI through a series resistor to limit the base current. Choose the resistor such that the minimum base current is greater than 1/20 of the peak inductor current. For example, assume VDD,MIN = 3V and IPK = 100mA; then RS 20 x (3 - 0.7) / 100mA = 460.
Charge-Pump Capacitor (Negative Output)
Possible negative output topologies are shown in Figures 5 and 6. Overall efficiency for the negative output configuration is less than for the positive output circuit because of the extra components in the powertransfer path. For efficient charge transfer, C4 must have low ESR and should be smaller than the output capacitor (C5). C4 sees the same voltage as C5, and should have the same voltage rating. A 1F ceramic capacitor is a practical choice for cost and performance considerations. 2.2F is suggested for Figure 6's circuit.
Feedback-Compensation Capacitor
The high value of the feedback resistors (R3, R4, R5, Figure 4) makes the feedback loop susceptible to phase lag because of the parasitic capacitance at the FB pin. To compensate for this, connect a capacitor (C6, Figure 4) in parallel with R5. The value of C6 depends on the parallel combination of R3, R4, R5, and the individual circuit layout. Typical values range from 33pF to 220pF.
Reference-Compensation Capacitor
The internal reference uses an external capacitor for frequency compensation. Connect a ceramic capacitor with a 0.1F minimum value between REF and ground.
Output Filter Capacitor
A 22F, 35V, low-ESR, surface-mount tantalum output capacitor is sufficient for most applications. Output ripple voltage is dominated by the peak switch current multiplied by the output capacitor's effective series resistance (ESR). 100mVp-p output ripple is a good target for the trade-off between cost and performance. Capacitors smaller than 22F may be used for light loads and lower peak current. Surface-mount capacitors are generally preferred because they lack the inductance and resistance of their through-hole equivalents. The AVX TPS series and the Sprague 593D and 595D series are good choices for low-ESR surfacemount tantalum capacitors. Moderate-performance aluminum-electrolytic or tantalum capacitors can be successfully substituted in costsensitive applications with low output current. Matsuo and Nichicon provide suitable choices.
PC Board Layout and Grounding
Due to high current levels and fast switching waveforms, proper PC board layout is essential. In particular, keep all traces short, especially those connected to the FB pin and those connecting N1, L1, D1, D2, C4, and C5. Place R3, R4, and R5 as close to the feedback pin as possible. Use a star ground configuration: connect the grounds of the input bypass capacitor, the output capacitor, and the switching transistor together, close to the IC's PGND pin. Tie AGND and PGND together at the chip.
18
______________________________________________________________________________________
Digitally Adjustable LCD Bias Supplies MAX1620/MAX1621
2V TO 12V
R1 360k
R8 10k D3 1N6263 (ANY SCHOTTKY) TO REF 3 5 11 7 4 1 2 6 12
C3 10F
L1 220H 12.5V TO 23.5V OUT Q1 MMBT2907 R7 150k VOUTSW R4 300k C6 100pF
R2 100k
3V TO 5.5V
C1 0.1F
C2 0.1F
U1 BATT POK VDD MAX1620 MAX1621 POL SHDN (SUS) DN (SDA) UP (SCL) REF AGND
LX DHI DLO PGND DOUT FB LCDON
14 16 15 13 10 9 8
RS 470
D1 MBRS0540+ Q1 MMBT4401LT1
C5 10F
R6 150k
R3 300k
R5 2.2M
( ) ARE FOR MAX1621. NOTE: CONNECTIONS TO DIGITAL INPUTS NOT SHOWN. OPTIONAL
Figure 10. Positive Output with Bipolar Switching Transistor
___________________________________________________Simplified Block Diagram
VDD AGND SHDN DN (SDA) UP (SCL) SHDN (SUS) POL REF 1.5V BANDGAP REFERENCE 1.0V DHI FB BATT ON-TIME CONTROL DLO PGND LCDON LX DIGITAL INTERFACE 5-BIT DAC DOUT BIAS
MAX1620 MAX1621
POK ( ) ARE FOR MAX1621 ONLY.
___________________Chip Information
TRANSISTOR COUNT: 341 SUBSTRATE CONNECTED TO AGND
______________________________________________________________________________________
19
Digitally Adjustable LCD Bias Supplies MAX1620/MAX1621
________________________________________________________Package Information
QSOP.EPS
20
______________________________________________________________________________________

▲Up To Search▲

Price & Availability of MAX1620

	To Download MAX1620 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .